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PCI/ASPM: Read and set up L1 substate capabilities
authorRajat Jain <rajatja@google.com>
Tue, 3 Jan 2017 06:34:12 +0000 (22:34 -0800)
committerBjorn Helgaas <bhelgaas@google.com>
Tue, 14 Feb 2017 23:44:12 +0000 (17:44 -0600)
commitb5a0a9b59c8185aebcd9a717e2e6258b58c72c06
tree5965432f559df890e710532bfc6c8ad0472c59d2tree | snapshot
parentb2103ccbb67e3ef0f7a75d21c989f9614ddbcacacommit | diff
PCI/ASPM: Read and set up L1 substate capabilities

The PCIe spec (r3.1, sec 7.33) says the L1 PM Substates Capability may be
implemented only in function 0.

Read the L1 substate capability structures of upstream and downstream
components of the link and set it up in the device structure.

[bhelgaas: add specific spec reference]
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/pcie/aspm.c diff | blob | history
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