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(parent: 1acdb3b) | patch
target/riscv: csr: Hook debug CSR read/write
authorBin Meng <bin.meng@windriver.com>
Thu, 21 Apr 2022 00:33:21 +0000 (08:33 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 22 Apr 2022 00:35:16 +0000 (10:35 +1000)
commitb6092544fcbe747c005db25c38d8081d281c79ad
tree9eb946406e188919f3603c486117f35e9dfbf10ctree | snapshot
parent1acdb3b013f4c13a9482cccd9765491f8ed8841ccommit | diff
target/riscv: csr: Hook debug CSR read/write

This adds debug CSR read/write support to the RISC-V CSR RW table.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-4-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c diff | blob | history
target/riscv/csr.c diff | blob | history
target/riscv/debug.c diff | blob | history
target/riscv/debug.h diff | blob | history
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