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[AArch64] Do 64-bit vector move of 0 and -1 by extracting from the 128-bit move
authorJohn Brawn <john.brawn@arm.com>
Thu, 25 Oct 2018 14:56:48 +0000 (14:56 +0000)
committerJohn Brawn <john.brawn@arm.com>
Thu, 25 Oct 2018 14:56:48 +0000 (14:56 +0000)
commitb79b03ee2a83e70fe4f18a5019f4838ad7e69675
tree05ea850f5c695b03425657e9c80609d71ab4c6a3
parent1b6f74f7adcbf0a84a45ff45152f23d3ed41ba9c
[AArch64] Do 64-bit vector move of 0 and -1 by extracting from the 128-bit move

Currently a vector move of 0 or -1 will use different instructions depending on
the size of the vector. Using a single instruction (the 128-bit one) for both
gives more opportunity for Machine CSE to eliminate instructions.

Differential Revision: https://reviews.llvm.org/D53579

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345270 91177308-0d34-0410-b5e6-96231b3b80d8
14 files changed:
lib/Target/AArch64/AArch64InstrInfo.td
test/CodeGen/AArch64/aarch64-be-bv.ll
test/CodeGen/AArch64/aarch64-smax-constantfold.ll
test/CodeGen/AArch64/arm64-neon-compare-instructions.ll
test/CodeGen/AArch64/arm64-neon-copy.ll
test/CodeGen/AArch64/arm64-vector-ext.ll
test/CodeGen/AArch64/arm64-vshuffle.ll
test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
test/CodeGen/AArch64/bitcast.ll
test/CodeGen/AArch64/fast-isel-cmp-vec.ll
test/CodeGen/AArch64/fold-constants.ll
test/CodeGen/AArch64/machine_cse.ll
test/CodeGen/AArch64/neon-compare-instructions.ll
test/CodeGen/AArch64/selectiondag-order.ll