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[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.
authorPuyan Lotfi <puyan@puyan.org>
Wed, 10 Jan 2018 00:56:48 +0000 (00:56 +0000)
committerPuyan Lotfi <puyan@puyan.org>
Wed, 10 Jan 2018 00:56:48 +0000 (00:56 +0000)
commitb931375195077d79330792590733db7de9a8f1bd
treed5780fb16246e9873c80f8473446e19200f7f930
parent52483265a57d78fe17a725129488c26ad138f9f5
[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.

Planning to add support for named vregs. This puts is in a conundrum since
physregs are named as well. To rectify this we need to use a sigil other than
'%' for physregs in MIR. We've settled on using '$' for physregs but first we
must repurpose it from external symbols using it, which is what this commit is
all about. We think '&' will have familiar semantics for C/C++ users.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322146 91177308-0d34-0410-b5e6-96231b3b80d8
40 files changed:
lib/CodeGen/MIRParser/MILexer.cpp
lib/CodeGen/MIRPrinter.cpp
lib/CodeGen/MachineOperand.cpp
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
test/CodeGen/AArch64/ldst-opt.mir
test/CodeGen/AArch64/spill-undef.mir
test/CodeGen/AMDGPU/hazard-inlineasm.mir
test/CodeGen/AMDGPU/hazard.mir
test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
test/CodeGen/ARM/Windows/vla-cpsr.ll
test/CodeGen/MIR/AArch64/spill-fold.mir
test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
test/CodeGen/MIR/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
test/CodeGen/MIR/ARM/cfi-same-value.mir
test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
test/CodeGen/MIR/Mips/memory-operands.mir
test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
test/CodeGen/MIR/X86/def-register-already-tied-error.mir
test/CodeGen/MIR/X86/early-clobber-register-flag.mir
test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
test/CodeGen/MIR/X86/external-symbol-operands.mir
test/CodeGen/MIR/X86/frame-info-stack-references.mir
test/CodeGen/MIR/X86/inline-asm-registers.mir
test/CodeGen/MIR/X86/inline-asm.mir
test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
test/CodeGen/MIR/X86/memory-operands.mir
test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
test/CodeGen/PowerPC/aantidep-def-ec.mir
test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
test/CodeGen/SystemZ/fp-cmp-07.mir
test/CodeGen/X86/stack-protector-weight.ll
unittests/CodeGen/MachineOperandTest.cpp