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(parent: 5b5c2a2) | patch
RISC-V: remove timer leftovers
authorChristoph Hellwig <hch@lst.de>
Sat, 4 Aug 2018 08:23:12 +0000 (10:23 +0200)
committerPalmer Dabbelt <palmer@sifive.com>
Mon, 13 Aug 2018 15:31:30 +0000 (08:31 -0700)
commitb9490350f751e5d17a24d0ae5af1f9e7f55c7c31
treefd0b8871c4c79a33885b709ed807fdcb29617952tree | snapshot
parent5b5c2a2c44d7225ab3abbcc7e1881b97ea9872ddcommit | diff
RISC-V: remove timer leftovers

This code is currently unused and will be added back later in a different
place with the real interrupt and clocksource support.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/kernel/time.c diff | blob | history
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