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(parent: 47fe36d) | patch
ARM64: Ensure stricter alignment when loading and storing register pairs
authorAnton Kirilov <anton.kirilov@linaro.org>
Fri, 10 Jun 2016 16:46:12 +0000 (17:46 +0100)
committerAnton Kirilov <anton.kirilov@linaro.org>
Tue, 28 Jun 2016 10:07:24 +0000 (11:07 +0100)
commitbde6ae1c6e1bc0ea1c8d80e3b0ec401517c6d7f7
treeb8b358dbab45a235af3413b6750db13419d81dc2tree | snapshot
parent47fe36d8dea0309e5ff08fc77244a371ba10d9dbcommit | diff
ARM64: Ensure stricter alignment when loading and storing register pairs

The impetus for this change is the fact that loads that cross a 64 byte
boundary and stores that cross a 16 byte boundary are a performance issue
on Cortex-A57 and A72.

Change-Id: I81263dc72272192ad2d190b741a955f175880461
compiler/optimizing/optimizing_cfi_test_expected.inc diff | blob | history
compiler/utils/arm64/assembler_arm64.cc diff | blob | history
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