[X86][SSE] Prevent misaligned non-temporal vector load/store combines

[X86][SSE] Prevent misaligned non-temporal vector load/store combines

For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway.

First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets.

Differential Revision: https://reviews.llvm.org/D63246

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363564 91177308-0d34-0410-b5e6-96231b3b80d8