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AMDGPU: Implement read_register and write_register intrinsics
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 26 Jan 2016 04:29:24 +0000 (04:29 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 26 Jan 2016 04:29:24 +0000 (04:29 +0000)
commitc024d32472269aab44bb6b553b7cb63d92bf849b
treed5621e016f3a6e9857fe63e0f602c1c4cbdf51df
parentf748e83708eb2b1d437f73221486a4dbeaf8a65e
AMDGPU: Implement read_register and write_register intrinsics

Some of the special intrinsics now that now correspond to a instruction
also have special setting of some registers, e.g. llvm.SI.sendmsg sets
m0 as well as use s_sendmsg. Using these explicit register intrinsics
may be a better option.

Reading the exec mask and others may be useful for debugging. For this
I'm not sure this is entirely correct because we would want this to
be convergent, although it's possible this is already treated
sufficently conservatively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258785 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/SIISelLowering.cpp
lib/Target/AMDGPU/SIISelLowering.h
test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/read_register.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/write_register.ll [new file with mode: 0644]