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drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail
authorDouglas Anderson <dianders@chromium.org>
Wed, 18 Dec 2019 22:35:29 +0000 (14:35 -0800)
committerNeil Armstrong <narmstrong@baylibre.com>
Thu, 13 Feb 2020 09:22:05 +0000 (10:22 +0100)
commitc2e1ea320d19262fb005adae191f574ae12a1508
treee57ccdcb921d65eef6887607bb4a965df9a9074c
parent3438ea3dc89603bd83819cd254acc32a50526497
drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail

If we fail training at a lower DP link rate let's now keep trying
until we run out of rates to try.  Basically the algorithm here is to
start at the link rate that is the theoretical minimum and then slowly
bump up until we run out of rates or hit the max rate of the sink.  We
query the sink using a DPCD read.

This is, in fact, important in practice.  Specifically at least one
panel hooked up to the bridge (AUO B116XAK01) had a theoretical min
rate more than 1.62 GHz (if run at 24 bpp) and fails to train at the
next rate (2.16 GHz).  It would train at 2.7 GHz, though.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191218143416.v3.8.I251add713bc5c97225200894ab110ea9183434fd@changeid
drivers/gpu/drm/bridge/ti-sn65dsi86.c