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[X86][SSE] Add support for lowering shuffles to PACKSS/PACKUS
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 3 Oct 2017 12:01:31 +0000 (12:01 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 3 Oct 2017 12:01:31 +0000 (12:01 +0000)
commitc527eca47f93e74924cafe53c542e4c36f417f79
tree8681c048cea30c3b2f1d9274effbe7bea25a5259
parent7bd839f42ba5100cd48dead581fdcad9523d0dee
[X86][SSE] Add support for lowering shuffles to PACKSS/PACKUS

If the upper bits of a truncation shuffle patterns have at least the minimum number of sign/zero bits on their inputs then we can safely use PACKSS/PACKUS as shuffles.

Partial fix for https://bugs.llvm.org/show_bug.cgi?id=34773

Differential Revision: https://reviews.llvm.org/D38472

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314788 91177308-0d34-0410-b5e6-96231b3b80d8
17 files changed:
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/avx-cvt-2.ll
test/CodeGen/X86/avx2-shift.ll
test/CodeGen/X86/avx2-vbroadcast.ll
test/CodeGen/X86/avx2-vector-shifts.ll
test/CodeGen/X86/avx512-any_extend_load.ll
test/CodeGen/X86/avx512-trunc.ll
test/CodeGen/X86/bitcast-and-setcc-256.ll
test/CodeGen/X86/bitcast-and-setcc-512.ll
test/CodeGen/X86/bitcast-setcc-128.ll
test/CodeGen/X86/psubus.ll
test/CodeGen/X86/shuffle-strided-with-offset-256.ll
test/CodeGen/X86/vector-compare-results.ll
test/CodeGen/X86/vector-shift-ashr-128.ll
test/CodeGen/X86/vector-trunc.ll
test/CodeGen/X86/vselect-avx.ll
test/CodeGen/X86/widen_arith-2.ll