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(parent: 98eaacd) | patch
[AMDGPU] Don't cluster stores
authorJay Foad <jay.foad@amd.com>
Wed, 3 Jun 2020 09:01:12 +0000 (10:01 +0100)
committerJay Foad <jay.foad@amd.com>
Mon, 14 Sep 2020 12:40:17 +0000 (13:40 +0100)
commitc799f873cb9feaea265aa3df8f3372949f8263d0
treec473b106be7671a831495f0afef053d38af5cef9tree | snapshot
parent98eaacd73d40eb28d5fa86bc3cfc9371581ee0cbcommit | diff
[AMDGPU] Don't cluster stores

Clustering loads has caching benefits, but as far as I know there is no
advantage to clustering stores on any AMDGPU subtargets.

The disadvantage is that it tends to increase register pressure and
restricts scheduling freedom.

Differential Revision: https://reviews.llvm.org/D85530
26 files changed:
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/call-argument-types.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/cluster_stores.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/fshr.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/half.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/memory_clause.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/merge-stores.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/store-local.128.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/store-local.96.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll diff | blob | history
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