Merge tag 'pull-riscv-to-apply-
20211220-1' of github.com:alistair23/qemu into staging
First RISC-V PR for QEMU 7.0
- Add support for ratified 1.0 Vector extension
- Drop support for draft 0.7.1 Vector extension
- Support Zfhmin and Zfh extensions
- Improve kernel loading for non-Linux platforms
# gpg: Signature made Sun 19 Dec 2021 08:56:08 PM PST
# gpg: using RSA key
F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-
20211220-1' of github.com:alistair23/qemu: (88 commits)
hw/riscv: Use load address rather than entry point for fw_dynamic next_addr
target/riscv: Enable bitmanip Zb[abcs] instructions
riscv: Set 5.4 as minimum kernel version for riscv32
target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
target/riscv: rvv-1.0: update opivv_vadc_check() comment
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
target/riscv: rvv-1.0: add vsetivli instruction
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
target/riscv: gdb: support vector registers for rv64 & rv32
target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
target/riscv: rvv-1.0: implement vstart CSR
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
target/riscv: add "set round to odd" rounding mode helper function
target/riscv: rvv-1.0: widening floating-point/integer type-convert
target/riscv: rvv-1.0: floating-point/integer type-convert instructions
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>