[X86][SSE] Improve lowering of vXi64 multiply with known zero 32-bit halves

[X86][SSE] Improve lowering of vXi64 multiply with known zero 32-bit halves

vXi64 multiplication is lowered into 3 calls of vpmuludq with the upper/lower 32-bit halves.

If any of these halves are zero then we can remove individual calls. Although there was isBuildVectorAllZeros code to do this I don't think it ever worked (maybe just for constant folded cases that don't seem to be tested for any longer).

This requires additional X86ISD support for computeKnownBitsForTargetNode, so far I've just added support for X86ISD::VZEXT (VPMOVZX* - helping the AVX2+ cases).

Partial fix for PR30845

Differential Revision: https://reviews.llvm.org/D26590

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287223 91177308-0d34-0410-b5e6-96231b3b80d8