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drm/i915/ringbuffer: Pull the render flush into breadcrumb emission
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 28 Dec 2018 15:31:14 +0000 (15:31 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Fri, 28 Dec 2018 16:36:57 +0000 (16:36 +0000)
commitcaa5915bb3c1e61bd895383364011a8921fee053
treeaa1fa823c6d7e024e998e3f58907e946072d35e2
parent6a6237293d0c02e0902b29a86e3e353e21f7bea6
drm/i915/ringbuffer: Pull the render flush into breadcrumb emission

In preparation for removing the manual EMIT_FLUSH prior to emitting the
breadcrumb implement the flush inline with writing the breadcrumb for
ringbuffer emission.

With a combined flush+breadcrumb, we can use a single operation to both
flush and after the flush is complete (post-sync) write the breadcrumb.
This gives us a strongly ordered operation that should be sufficient to
serialise the write before we emit the interrupt; and therefore we may
take the opportunity to remove the irq_seqno_barrier w/a for gen6+.
Although using the PIPECONTROL to write the breadcrumb is slower than
MI_STORE_DWORD_IMM, by combining the operations into one and removing the
extra flush (next patch) it is faster

For gen2-5, we simply combine the MI_FLUSH into the breadcrumb emission,
though maybe we could find a solution here to the seqno-vs-interrupt
issue on Ironlake by mixing up the flush? The answer is no, adding an
MI_FLUSH before the interrupt is insufficient.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181228153114.4948-2-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/intel_ringbuffer.c