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(parent: e583e65) | patch
media: ccs-pll: Add support for lane speed model
authorSakari Ailus <sakari.ailus@linux.intel.com>
Mon, 22 Jun 2020 10:16:24 +0000 (12:16 +0200)
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Mon, 7 Dec 2020 14:52:09 +0000 (15:52 +0100)
commitcac8f5d28e56c405befd1613fc38c962aaf69f30
treedb75fe3b01234730fee1d89847e102a49c5ebc3atree | snapshot
parente583e654565fd12e45d8cef64dcdd80e2902ac13commit | diff
media: ccs-pll: Add support for lane speed model

CCS PLL includes a capability to calculate the VT clocks on per-lane
basis. Add support for this feature.

Move calculation of the pixel rate on the CSI-2 bus early in the function
as everything needed to calculate it is already available.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
drivers/media/i2c/ccs-pll.c diff | blob | history
drivers/media/i2c/ccs-pll.h diff | blob | history
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