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(parent: b261509) | patch
drm/amd/display: fix dcn315 memory channel count and width read
authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tue, 30 Aug 2022 19:16:40 +0000 (15:16 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 21 Sep 2022 21:18:39 +0000 (17:18 -0400)
commitcb0eca01ad9756e853efec3301203c2b5b45aa9f
tree1217831d7c695ab029a23ef74a8d5c3cdd912a1etree | snapshot
parentb261509952bc19d1012cf732f853659be6ebc61ecommit | diff
drm/amd/display: fix dcn315 memory channel count and width read

[Why & How]
Correctly set ddr5 channel width to 8 bytes

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c diff | blob | history
This is a test repository.
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