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(parent: cf83a28) | patch
clk: tegra20/30: Don't pre-initialize displays parent clock
authorDmitry Osipenko <digetx@gmail.com>
Wed, 18 Dec 2019 18:44:06 +0000 (21:44 +0300)
committerThierry Reding <treding@nvidia.com>
Fri, 10 Jan 2020 14:50:25 +0000 (15:50 +0100)
commitcb98598e68aa6c812d4ee4abb8f69dafecba64bc
tree5449083286a22c9f061a9e36e40836a74266a548tree | snapshot
parentcf83a28f281fb3cce090e1b99d31b26baef9c13bcommit | diff
clk: tegra20/30: Don't pre-initialize displays parent clock

Both Tegra20 and Tegra30 are initializing display's parent clock
incorrectly because PLLP is running at 216/408MHz while display rate is
set to 600MHz, but pre-setting the parent isn't needed at all because
display driver selects proper parent anyways.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra20.c diff | blob | history
drivers/clk/tegra/clk-tegra30.c diff | blob | history
This is a test repository.
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