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(parent: c5cf6c8) | patch
[MIRParser] Allow generic register specification on operand.
authorAhmed Bougacha <ahmed.bougacha@gmail.com>
Fri, 20 Jan 2017 00:29:59 +0000 (00:29 +0000)
committerAhmed Bougacha <ahmed.bougacha@gmail.com>
Fri, 20 Jan 2017 00:29:59 +0000 (00:29 +0000)
commitcbd2ff78c0c102dec2a029258fa16e11dc4ea3ed
tree739e9273a972898f948edfd451e3969bb12b777etree | snapshot
parentc5cf6c8ad5c7147ccd28e13a5855fa20ae78c2fbcommit | diff
[MIRParser] Allow generic register specification on operand.

This completes r292321 by adding support for generic registers, e.g.:

  %2:_(s32) = G_ADD %0, %1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292550 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/MIRParser/MIParser.cpp diff | blob | history
test/CodeGen/MIR/X86/register-operand-class.mir diff | blob | history
external/llvm
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