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PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM
authorHonghui Zhang <honghui.zhang@mediatek.com>
Fri, 1 Feb 2019 05:36:07 +0000 (13:36 +0800)
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Fri, 1 Mar 2019 11:22:21 +0000 (11:22 +0000)
commitcbe3a7728c7ad4721677208e155db06f67eb57d2
tree919e48c3264e73bfbb411f0cc2e38018586a6417
parentc61df57343bf05743f8abbb31eec9a6f05820dd1
PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM

The PCIE_AXI_WINDOW0 register defines the inbound window size for
requests coming from PCI endpoints. Requests outside of this window will
be treated as unsupported requests.

Enlarge this window size from 2^31 to 2^33 to support a 8GB address
space (which gives endpoints DMA access to full 4GB DRAM address range
- physical DRAM starts at 0x40000000).

Reported-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
drivers/pci/controller/pcie-mediatek.c