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intel_iommu: dma read/write draining support
authorPeter Xu <peterx@redhat.com>
Mon, 17 Dec 2018 07:31:12 +0000 (15:31 +0800)
committerMichael S. Tsirkin <mst@redhat.com>
Wed, 19 Dec 2018 21:48:16 +0000 (16:48 -0500)
commitccc23bb08a84f3709b08cc10ffd4e819832fae6d
tree5bfcce0fb1b9f10714940bf1ce638693c1b7b0be
parent095955b24d25715f38b78703dc0a295761bffaca
intel_iommu: dma read/write draining support

Support DMA read/write draining should be easy for existing VT-d
emulation since the emulation itself does not have any request queue
there so we don't need to do anything to flush the un-commited queue.
What we need to do is to declare the support.

These capabilities are required to pass Windows SVVP test program.  It
is verified that when with parameters "x-aw-bits=48,caching-mode=off"
we can pass the Windows SVVP test with this patch applied.  Otherwise
we'll fail with:

        IOMMU[0] - DWD (DMA write draining) not supported
        IOMMU[0] - DWD (DMA read draining) not supported
        Segment 0 has no DMA remapping capable IOMMU units

However since these bits are not declared support for QEMU<=3.1, we'll
need a compatibility bit for it and we turn this on by default only
for QEMU>=4.0.

Please refer to VT-d spec 6.5.4 for more information.

CC: Yu Wang <wyu@redhat.com>
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1654550
Signed-off-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
hw/i386/intel_iommu.c
hw/i386/intel_iommu_internal.h
include/hw/i386/intel_iommu.h
include/hw/i386/pc.h