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target/i386: implement F16C instructions
authorPaolo Bonzini <pbonzini@redhat.com>
Wed, 19 Oct 2022 11:22:06 +0000 (13:22 +0200)
committerPaolo Bonzini <pbonzini@redhat.com>
Thu, 20 Oct 2022 13:16:18 +0000 (15:16 +0200)
commitcf5ec6641ed456e2748b211b7bbf5103bfc93098
tree84e5a3c059e7de484c1c7d66714c68e8d60ca9e1
parent314d3eff66f41f39191aaca2e5f6e3dc81480c1b
target/i386: implement F16C instructions

F16C only consists of two instructions, which are a bit peculiar
nevertheless.

First, they access only the low half of an YMM or XMM register for the
packed-half operand; the exact size still depends on the VEX.L flag.
This is similar to the existing avx_movx flag, but not exactly because
avx_movx is hardcoded to affect operand 2.  To this end I added a "ph"
format name; it's possible to reuse this approach for the VPMOVSX and
VPMOVZX instructions, though that would also require adding two more
formats for the low-quarter and low-eighth of an operand.

Second, VCVTPS2PH is somewhat weird because it *stores* the result of
the instruction into memory rather than loading it.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/i386/cpu.c
target/i386/cpu.h
target/i386/ops_sse.h
target/i386/ops_sse_header.h
target/i386/tcg/decode-new.c.inc
target/i386/tcg/decode-new.h
target/i386/tcg/emit.c.inc
tests/tcg/i386/test-avx.c
tests/tcg/i386/test-avx.py