[DAGCombiner] Teach createBuildVecShuffle to handle cases where input vectors are...

[DAGCombiner] Teach createBuildVecShuffle to handle cases where input vectors are less than half of the output vector size.

This will be needed by a future commit to support sign/zero extending from v8i8 to v8i64 which requires a sign/zero_extend_vector_inreg to be created which requires v8i8 to be concatenated upto v64i8 and goes through this code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284204 91177308-0d34-0410-b5e6-96231b3b80d8