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(parent: 8018903) | patch
target-ppc: Correct LE Host Inversion of Lower VSRs
authorTom Musta <tommusta@gmail.com>
Mon, 31 Mar 2014 21:03:58 +0000 (16:03 -0500)
committerAlexander Graf <agraf@suse.de>
Tue, 8 Apr 2014 09:20:02 +0000 (11:20 +0200)
commitd359db00e6dfaf12cbdedd30e36f879110d4f9d1
treef1b4d414461d61fada01daacc59d2a29783af873tree | snapshot
parent80189035de73f30e42a7f933c45cccfc4b0c56e9commit | diff
target-ppc: Correct LE Host Inversion of Lower VSRs

This change properly orders the doublewords of the VSRs 0-31.  Because these
registers are constructed from separate doublewords, they must be inverted
on Little Endian hosts.  The inversion is performed both when the VSR is read
and when it is written.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Tested-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc/fpu_helper.c diff | blob | history
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