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clk: renesas: r9a09g011: Add TIM clock and reset entries
authorBiju Das <biju.das.jz@bp.renesas.com>
Mon, 5 Dec 2022 14:59:50 +0000 (14:59 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 27 Dec 2022 08:42:44 +0000 (09:42 +0100)
commitd459f557ad76f449687e76fcb94f1009551dd669
treec54f7e7bf2d82658ff837da3db44a85f2a332716
parentff1dd4a8422beebbc5df98671fcd0ad47c57b7b2
clk: renesas: r9a09g011: Add TIM clock and reset entries

Add Compare-Match Timer (TIM) clock and reset entries to CPG
driver.

The TIM IP on the RZ/V2M comes with 32 channels, but the ISP has
full control of channels 0 to 7, and channels 24 to 31. Therefore
Linux is only allowed to use channels 8 to 23.

The TIM has shared peripheral clock with other modules, so mark it
as critical clock.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221205145955.391526-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g011-cpg.c