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[Hexagon] Generate instructions for operations on predicate registers
authorKrzysztof Parzyszek <kparzysz@codeaurora.org>
Tue, 14 Jul 2015 19:30:21 +0000 (19:30 +0000)
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>
Tue, 14 Jul 2015 19:30:21 +0000 (19:30 +0000)
commitd496e176f065e5ae7be6baf6ff5352b222d5665e
treea9e1c5cc7dc6f3a4695986522fddebad7aafeab7tree | snapshot
parent890c16626f63ca0978b705e173ed9e5a0068d418commit | diff
[Hexagon] Generate instructions for operations on predicate registers

Convert logical operations on general-purpose registers to the correspon-
ding operations on predicate registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242186 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Hexagon/CMakeLists.txt diff | blob | history
lib/Target/Hexagon/HexagonGenPredicate.cpp [new file with mode: 0644] blob
lib/Target/Hexagon/HexagonTargetMachine.cpp diff | blob | history
test/CodeGen/Hexagon/predicate-logical.ll [new file with mode: 0644] blob
test/CodeGen/Hexagon/predicate-rcmp.ll [new file with mode: 0644] blob
external/llvm
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