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clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
authorBiju Das <biju.das.jz@bp.renesas.com>
Fri, 2 Jul 2021 13:50:03 +0000 (14:50 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 19 Jul 2021 08:53:53 +0000 (10:53 +0200)
commitd520af345189c04095bdd256d3601864601ac562
tree29b382f29d19f261315dc596d26b8791c7525a5atree | snapshot
parent03fa6e4b2622035389a4beb9699551d63d130493commit | diff
clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries

Add SSIF-2 clock and reset entries in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210702135010.5937-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
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