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[AMDGPU] Increased vector length for global/constant loads.
authorMark Searles <m.c.searles@gmail.com>
Mon, 19 Feb 2018 16:42:49 +0000 (16:42 +0000)
committerMark Searles <m.c.searles@gmail.com>
Mon, 19 Feb 2018 16:42:49 +0000 (16:42 +0000)
commitdb070bbdacd303ae7da129f59beaf35024d94c53
treedee39897067d5baa7cd0d4cb420573c3e65f2e3f
parent7c93b6c31caa3d1bd2bf88dddb4ee290346557af
[AMDGPU] Increased vector length for global/constant loads.

Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache; loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords.

Author: FarhanaAleen

Reviewed By: rampitec

Subscribers: llvm-commits, AMDGPU

Differential Revision: https://reviews.llvm.org/D43275

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325518 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
test/CodeGen/AMDGPU/load-constant-f32.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/load-constant-f64.ll
test/CodeGen/AMDGPU/waitcnt-looptest.ll