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[globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings...
authorDaniel Sanders <daniel_l_sanders@apple.com>
Sat, 28 Apr 2018 18:14:50 +0000 (18:14 +0000)
committerDaniel Sanders <daniel_l_sanders@apple.com>
Sat, 28 Apr 2018 18:14:50 +0000 (18:14 +0000)
commitdc03441296984f1d836273a500110c5b6cca6122
tree10d7288c603e0f99ceea6150309649c43c1dcc06
parentcb99414531493c436f39093ff692fafb6833cb25
[globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings for them

Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
  registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
  extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
  improve optimization of extends and truncates, this legality requirement
  would spread without considerable care w.r.t when certain combines were
  permitted.
* The SelectionDAG importer required some ugly and fragile pattern
  rewriting to translate patterns into this style.

This patch begins changing the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.

This patch introduces the new generic instructions and new variation on
G_LOAD and adds lowering for them to convert back to the existing
representations.

Depends on D45466

Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, aemerson, javed.absar

Reviewed By: aemerson

Subscribers: aemerson, kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D45540

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331115 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
include/llvm/Support/TargetOpcodes.def
include/llvm/Target/GenericOpcodes.td
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
lib/Target/AArch64/AArch64LegalizerInfo.cpp
test/CodeGen/AArch64/GlobalISel/legalize-extload.mir [new file with mode: 0644]
test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir [new file with mode: 0644]
test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir [new file with mode: 0644]