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[DAG] Avoid smart constructor-based dangling nodes.
authorNirav Dave <niravd@google.com>
Tue, 26 Mar 2019 15:08:14 +0000 (15:08 +0000)
committerNirav Dave <niravd@google.com>
Tue, 26 Mar 2019 15:08:14 +0000 (15:08 +0000)
commitde6ac6d2115ec3c3ad611967ce88917ec5c49aec
treefa563ed900c510d2b837ae64d225f847cb802bd3
parent1b75f131c6748481d8dd4109db4fe90ce13c7d74
[DAG] Avoid smart constructor-based dangling nodes.

Various SelectionDAG non-combine operations (e.g. the getNode smart
constructor and legalization) may leave dangling nodes by applying
optimizations or not fully pruning unused result values. This can
result in nodes that are never added to the worklist and therefore can
not be pruned.

Add a node inserter as the current node deleter to make sure such
nodes have the chance of being pruned.

Many minor changes, mostly positive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356996 91177308-0d34-0410-b5e6-96231b3b80d8
49 files changed:
include/llvm/CodeGen/SelectionDAG.h
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask-const.ll
test/CodeGen/ARM/CGP/arm-cgp-icmps.ll
test/CodeGen/ARM/arm-storebytesmerge.ll
test/CodeGen/ARM/vdup.ll
test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
test/CodeGen/X86/3addr-or.ll
test/CodeGen/X86/avx-load-store.ll
test/CodeGen/X86/midpoint-int-vec-128.ll
test/CodeGen/X86/oddshuffles.ll
test/CodeGen/X86/psubus.ll
test/CodeGen/X86/sadd_sat_vec.ll
test/CodeGen/X86/sat-add.ll
test/CodeGen/X86/select_const.ll
test/CodeGen/X86/shuffle-strided-with-offset-512.ll
test/CodeGen/X86/shuffle-vs-trunc-512-widen.ll
test/CodeGen/X86/shuffle-vs-trunc-512.ll
test/CodeGen/X86/ssub_sat_vec.ll
test/CodeGen/X86/uadd_sat_vec.ll
test/CodeGen/X86/umul_fix.ll
test/CodeGen/X86/unfold-masked-merge-vector-variablemask-const.ll
test/CodeGen/X86/usub_sat_vec.ll
test/CodeGen/X86/vec_minmax_sint.ll
test/CodeGen/X86/vec_minmax_uint.ll
test/CodeGen/X86/vector-narrow-binop.ll
test/CodeGen/X86/vector-reduce-smax-widen.ll
test/CodeGen/X86/vector-reduce-smax.ll
test/CodeGen/X86/vector-reduce-smin-widen.ll
test/CodeGen/X86/vector-reduce-smin.ll
test/CodeGen/X86/vector-reduce-umax-widen.ll
test/CodeGen/X86/vector-reduce-umax.ll
test/CodeGen/X86/vector-reduce-umin-widen.ll
test/CodeGen/X86/vector-reduce-umin.ll
test/CodeGen/X86/vector-shuffle-128-v8.ll
test/CodeGen/X86/vector-shuffle-256-v16.ll
test/CodeGen/X86/vector-trunc-packus-widen.ll
test/CodeGen/X86/vector-trunc-packus.ll
test/CodeGen/X86/vector-trunc-ssat-widen.ll
test/CodeGen/X86/vector-trunc-ssat.ll
test/CodeGen/X86/vector-trunc-usat-widen.ll
test/CodeGen/X86/vector-trunc-usat.ll
test/CodeGen/X86/vsel-cmp-load.ll
test/CodeGen/X86/zext-demanded.ll
test/CodeGen/X86/zext-logicop-shift-load.ll