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[X86] Teach lowering to only let through (insert_subvector (vXi1 zeros), subvec,...
authorCraig Topper <craig.topper@intel.com>
Fri, 8 Dec 2017 20:10:33 +0000 (20:10 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 8 Dec 2017 20:10:33 +0000 (20:10 +0000)
commitdf810d268db7517782862f23de640ffa03a4b124
tree53d8b7218f06d0b2d53e44ad27594e8d9a07b5fb
parent238512c3f88b218af7f30acf1f06d8bf456ae5d3
[X86] Teach lowering to only let through (insert_subvector (vXi1 zeros), subvec, 0) for vector sizes that have native KSHIFT support.

For narrow sizes we'll widen the zero vector and widen the insert. Then do an extract_subvector to get back down to correct size.

This allows us to remove some patterns from the isel table that had to COPY_TO_REGCLASS to an oversized register, do the shift and then COPY_TO_REGCLASS back to the narrow register. Now this is represented explicitly in the DAG.

This seems to have perturbed the register allocation in one of the tests, but the number of instructions didn't change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320190 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrVecCompiler.td
test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll