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clk: renesas: r8a7795: Fix SD clocks
authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Wed, 10 Aug 2016 07:29:43 +0000 (09:29 +0200)
committerStephen Boyd <sboyd@codeaurora.org>
Fri, 12 Aug 2016 00:47:56 +0000 (17:47 -0700)
commite0cb1b84163720ec67ff0e54397fd3f57ad4a4dd
tree66f09380156b7555002f2396db771c2d18568362
parented0ab110235c659fdb3f73d27907b1b45b89cf30
clk: renesas: r8a7795: Fix SD clocks

According to the datasheet, SDn clocks are from the SDSRC clock. And
the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal
core clock. Otherwise, since the sdhi driver will calculate clock for
a sd card using the wrong parent clock rate, and then performance will
be not good.

Fixes: 90c073e53909da85 ("clk: shmobile: r8a7795: Add SD divider support")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/renesas/r8a7795-cpg-mssr.c