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ARM: tegra: apalis-tk1: reorder cpu dfll clock properties
authorMarcel Ziswiler <marcel.ziswiler@toradex.com>
Sat, 1 Sep 2018 13:04:57 +0000 (15:04 +0200)
committerThierry Reding <treding@nvidia.com>
Wed, 26 Sep 2018 14:50:38 +0000 (16:50 +0200)
commite0cffa9a1b64099f537887712ba3802f92429675
tree11a0b1aef873a965d1d0f919a65ce5944bae4c8btree | snapshot
parenta052d2b67f00dfc6181d7dea6ff911bc7175f52acommit | diff
ARM: tegra: apalis-tk1: reorder cpu dfll clock properties

Reorder CPU DFLL clock properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi diff | blob | history
arch/arm/boot/dts/tegra124-apalis.dtsi diff | blob | history
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