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clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE
authorLeonard Crestez <leonard.crestez@nxp.com>
Fri, 22 Nov 2019 21:45:01 +0000 (23:45 +0200)
committerShawn Guo <shawnguo@kernel.org>
Mon, 9 Dec 2019 01:15:26 +0000 (09:15 +0800)
commite18f64712e9ef22054da1babe425d2a5892edcd4
tree7631e7979f5942135e50dec9fc459c0897285011
parentd9ea9ca2b420123557eca0490295cb4f48615ee2
clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE

DRAM frequency switches are executed in firmware and can change the
configuration of the DRAM PLL outside linux. Mark these CLKs with
CLK_GET_RATE_NOCACHE so we always read back the PLL config registers and
recalculate rates.

In current DRAM frequency tables on 8mm/8mn only the maximum frequency
uses the PLL so it's always configured in the same way. However reading
back the PLL configuration is the correct behavior and allows additional
setpoints in the future.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-imx8mm.c
drivers/clk/imx/clk-imx8mn.c
drivers/clk/imx/clk-pll14xx.c
drivers/clk/imx/clk.h