OSDN Git Service

target/riscv: add Ventana's Veyron V1 CPU
authorRahul Pathak <rpathak@ventanamicro.com>
Tue, 18 Apr 2023 12:36:24 +0000 (09:36 -0300)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 5 May 2023 00:49:50 +0000 (10:49 +1000)
commite1d084a8524a9225a46d485e2d164bb258f326f7
treeabcadf8bdb3ca76b673293db787c9aa42c492b30
parent190e9f8ec1b79f22097e9bf4aaa93aad7bd7fe69
target/riscv: add Ventana's Veyron V1 CPU

Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs
exclusively for the rv64 target. It's tested with the 'virt' board.

CPU specs and general information can be found here:

https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/

Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230418123624.16414-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu-qom.h
target/riscv/cpu.c
target/riscv/cpu_vendorid.h