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author	Michael Munday <mike.munday@lowrisc.org>
	Wed, 9 Dec 2020 19:41:19 +0000 (19:41 +0000)
committer	Luís Marques <luismarques@lowrisc.org>
	Wed, 9 Dec 2020 19:42:49 +0000 (19:42 +0000)
commit	e28b6a60bc02d61e50e0da545f337ea482b10240
tree	ce075909290fbd1aa3853583fe152185e5c0aa3e	tree \| snapshot
parent	ea981165a4ef2d6e8be0655f04cc4b61604db6d4	commit \| diff

[RISCV][NFC] Regenerate RISCV CodeGen tests

Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and added @plt to
some symbols.

Differential Revision: https://reviews.llvm.org/D92841

86 files changed:

llvm/test/CodeGen/RISCV/alloca.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/analyze-branch.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/atomic-load-store.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/atomic-rmw.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/byval.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/callee-saved-gprs.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-lp64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calls.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/copysign-casts.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/div.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-br-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-calling-conv.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-convert.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-frem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-mem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-previous-failure.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/exception-pointer-register.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/fastcc-float.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/fastcc-int.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-br-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-convert.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-frem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-mem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/fp128.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/fp16-promote.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/frame-info.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/frame.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/ghccc-rv32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/ghccc-rv64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-br-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-convert.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-mem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/interrupt-attr.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/large-stack.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/mul.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/remat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv32Zbb.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64-large-stack.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64Zbb.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64i-complex-float.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/select-and.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/select-or.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/shadowcallstack.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/shifts.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/shrinkwrap.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/split-sp-adjust.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/srem-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/srem-vector-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/stack-realignment.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/stack-store-check.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/tls-models.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/urem-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/urem-vector-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/vararg.ll		diff \| blob \| history

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