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[globalisel][tablegen] Split atomic load/store into separate opcode and enable for...
authorDaniel Sanders <daniel_l_sanders@apple.com>
Mon, 4 Dec 2017 20:39:32 +0000 (20:39 +0000)
committerDaniel Sanders <daniel_l_sanders@apple.com>
Mon, 4 Dec 2017 20:39:32 +0000 (20:39 +0000)
commite35711676bd03eb1caf7a9cb41179d82121c0457
tree7f503474d78f64753f5e7b7775e0a3753748a0f6
parent07f4dc367b2fe397d356114da57ed58556ad231c
[globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.

This patch splits atomics out of the generic G_LOAD/G_STORE and into their own
G_ATOMIC_LOAD/G_ATOMIC_STORE. This is a pragmatic decision rather than a
necessary one. Atomic load/store has little in implementation in common with
non-atomic load/store. They tend to be handled very differently throughout the
backend. It also has the nice side-effect of slightly improving the common-case
performance at ISel since there's no longer a need for an atomicity check in the
matcher table.

All targets have been updated to remove the atomic load/store check from the
G_LOAD/G_STORE path. AArch64 has also been updated to mark
G_ATOMIC_LOAD/G_ATOMIC_STORE legal.

There is one issue with this patch though which also affects the extending loads
and truncating stores. The rules only match when an appropriate G_ANYEXT is
present in the MIR. For example,
  (G_ATOMIC_STORE (G_TRUNC:s16 (G_ANYEXT:s32 (G_ATOMIC_LOAD:s16 X))))
will match but:
  (G_ATOMIC_STORE (G_ATOMIC_LOAD:s16 X))
will not. This shouldn't be a problem at the moment, but as we get better at
eliminating extends/truncates we'll likely start failing to match in some
cases. The current plan is to fix this in a patch that changes the
representation of extending-load/truncating-store to allow the MMO to describe
a different type to the operation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319691 91177308-0d34-0410-b5e6-96231b3b80d8
15 files changed:
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
include/llvm/CodeGen/TargetOpcodes.def
include/llvm/Target/GenericOpcodes.td
include/llvm/Target/GlobalISel/SelectionDAGCompat.td
lib/CodeGen/GlobalISel/IRTranslator.cpp
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
lib/Target/AArch64/AArch64InstructionSelector.cpp
lib/Target/AArch64/AArch64LegalizerInfo.cpp
lib/Target/ARM/ARMInstructionSelector.cpp
lib/Target/X86/X86InstructionSelector.cpp
test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
test/TableGen/GlobalISelEmitter.td
utils/TableGen/GlobalISelEmitter.cpp