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[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits
authorAlex Bradbury <asb@lowrisc.org>
Wed, 18 Apr 2018 20:34:23 +0000 (20:34 +0000)
committerAlex Bradbury <asb@lowrisc.org>
Wed, 18 Apr 2018 20:34:23 +0000 (20:34 +0000)
commite50f5775ba4b53b59aa1debaa4662479b23e8f09
tree46d578b49cc6b854c4abcec2f0e7dcf2d6b669f4
parent54ecebc52f7cfef4126c5b85205811e1c1d28dc5
[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits

These immediates can be materialised with just an lui, rather than an lui+addi
pair.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330293 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/RISCV/RISCVInstrInfo.td
test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
test/CodeGen/RISCV/calling-conv.ll
test/CodeGen/RISCV/float-arith.ll
test/CodeGen/RISCV/imm.ll
test/CodeGen/RISCV/vararg.ll