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[X86] Add a pattern for (i64 (and (anyext def32:), 0x00000000FFFFFFFF)) to produce...
authorCraig Topper <craig.topper@intel.com>
Sun, 27 Jan 2019 03:37:05 +0000 (03:37 +0000)
committerCraig Topper <craig.topper@intel.com>
Sun, 27 Jan 2019 03:37:05 +0000 (03:37 +0000)
commite7c0c5071f9f244f2f5b2831ae8343d6d9c8d69c
treeb154dabb995f6f76bb119089f8ae42a4d8a36e50tree | snapshot
parentb1650507d25d28a03f30626843b7b133796597b4commit | diff
[X86] Add a pattern for (i64 (and (anyext def32:), 0x00000000FFFFFFFF)) to produce SUBREG_TO_REG

def32 here means the producing instruction zeroed bits 63:32. We already do this for zext, but it looks like we can get an and+anyext sometimes.

Spotted in the diffs from D33587.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352303 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86InstrCompiler.td diff | blob | history
test/CodeGen/X86/zext-logicop-shift-load.ll diff | blob | history
external/llvm
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