ARM: dts: imx6qdl-dhcom: Align PHY reset timing with other DHCOM SoMs

ARM: dts: imx6qdl-dhcom: Align PHY reset timing with other DHCOM SoMs

According to datasheet Microchip LAN8710A/LAN8710Ai DS00002164B [1]
the reset should stay asserted for at least 100uS and software
should wait at least 200nS. On other DHCOM SoMs with the SMSC
LAN8710Ai PHY both reset delays are 500us. This should be plenty
and for consistency, the i.MX6 SoM should also use these delays.

[1] https://ww1.microchip.com/downloads/en/DeviceDoc/00002164B.pdf

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>