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author	Craig Topper <craig.topper@intel.com>
	Mon, 19 Mar 2018 19:00:32 +0000 (19:00 +0000)
committer	Craig Topper <craig.topper@intel.com>
	Mon, 19 Mar 2018 19:00:32 +0000 (19:00 +0000)
commit	e7f0446eb91a837f15a93e92a8892887c83caff8
tree	c3d91bd00a0195a812f36649e96c680e0016485d	tree \| snapshot
parent	369474116d7c114d644f82a516defb38d6afa40a	commit \| diff

[X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skylake scheduler models.

JRCXZ was already present, but not the others.

We never codegen this instruction so this doesn't affect much just trying to get them all into a single generated scheduler class in the output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327881 91177308-0d34-0410-b5e6-96231b3b80d8

external/llvm

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lib/Target/X86/X86SchedBroadwell.td		diff \| blob \| history
lib/Target/X86/X86SchedHaswell.td		diff \| blob \| history
lib/Target/X86/X86SchedSandyBridge.td		diff \| blob \| history
lib/Target/X86/X86SchedSkylakeClient.td		diff \| blob \| history
lib/Target/X86/X86SchedSkylakeServer.td		diff \| blob \| history
test/CodeGen/X86/schedule-x86_32.ll		diff \| blob \| history
test/CodeGen/X86/schedule-x86_64.ll		diff \| blob \| history