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target/riscv: Fix relationship between V, Zve*, F and D
authorWeiwei Li <liweiwei@iscas.ac.cn>
Wed, 15 Feb 2023 02:05:30 +0000 (10:05 +0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 1 Mar 2023 23:12:49 +0000 (15:12 -0800)
commite7f0a803a7b98a784ec6bce7992b7ad643881150
tree17877e3f155b691363eb584d8a32099ca8b45178tree | snapshot
parenta7336161f025c114fc57595801a492d8222540eccommit | diff
target/riscv: Fix relationship between V, Zve*, F and D

Add dependence chain:
*  V => Zve64d => Zve64f => Zve32f => F
*  V => Zve64d => D

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-6-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
target/riscv/cpu.c diff | blob | history
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