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drm: dsi: Add lane clock rate fields to DSI device
authorLinus Walleij <linus.walleij@linaro.org>
Tue, 23 Oct 2018 07:24:22 +0000 (09:24 +0200)
committerLinus Walleij <linus.walleij@linaro.org>
Wed, 24 Oct 2018 14:26:35 +0000 (16:26 +0200)
commite982e3f02071473cd1211e26cbe74a56b5be0aa0
tree8194fb21d45713281a7d86a6d29871413317d034
parent9edb6a0b206cb46782f9e74be035894bff9e0064
drm: dsi: Add lane clock rate fields to DSI device

The DSI devices have a maximum operating frequency specified
in their data sheet per the MIPI specification, and DSI hosts
that can scale their frequency need this information to set
their clock dividers right.

As current panel drivers often lack this information, specify
that setting it to zero will make the DSI host use some
reasonable default.

Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20181023072422.25754-1-linus.walleij@linaro.org
include/drm/drm_mipi_dsi.h