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drm/amd/display: Fix updating infoframe for DCN3.1 eDP
authorNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Wed, 16 Jun 2021 21:11:12 +0000 (17:11 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 13 Jul 2021 15:48:10 +0000 (11:48 -0400)
commite9cfe00ba8bd437da149a3c52712d4a73e249f45
treee2a9b302f682bd042f9ccccd28dc2f14bd85cc62
parent43a44c5322d1030d8f36ad679307c61f5b4e3716
drm/amd/display: Fix updating infoframe for DCN3.1 eDP

[Why]
We're only treating TMDS as a valid target for infoframe updates which
results in PSR being unable to transition from state 4 to state 5.

[How]
Also allow infoframe updates for DCN3.1 - following how we handle
this path for earlier ASIC as well.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c