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target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES
authorLike Xu <like.xu@linux.intel.com>
Fri, 29 May 2020 07:43:47 +0000 (15:43 +0800)
committerPaolo Bonzini <pbonzini@redhat.com>
Wed, 10 Jun 2020 16:10:47 +0000 (12:10 -0400)
commitea39f9b643959d759b8643b4c11c4cbb3683d0ff
treebda67282f3ebe87b29e742ca9c3acea7967ee13f
parent20c8fa2ec74fe32a42008c177ed9c48031356705
target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES

The Perfmon and Debug Capability MSR named IA32_PERF_CAPABILITIES is
a feature-enumerating MSR, which only enumerates the feature full-width
write (via bit 13) by now which indicates the processor supports IA32_A_PMCx
interface for updating bits 32 and above of IA32_PMCx.

The existence of MSR IA32_PERF_CAPABILITIES is enumerated by CPUID.1:ECX[15].

Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20200529074347.124619-5-like.xu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/i386/cpu.c
target/i386/cpu.h
target/i386/kvm.c