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clk: sunxi: Add support for table-based divider clocks
authorChen-Yu Tsai <wens@csie.org>
Thu, 26 Jun 2014 15:55:42 +0000 (23:55 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Fri, 4 Jul 2014 10:05:13 +0000 (12:05 +0200)
commitea5671bffbb2b6eefdce7e467a162ae2eef032ac
treedd3d35bcbe814cdb2d311921ee4b6a78d8747ea0
parent9a5e6c7eb5ccbb5f0d3a1dffce135f0a727f40e1
clk: sunxi: Add support for table-based divider clocks

A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.

This patch adds support for optional divider tables,
so the clock framework will know about the odd values.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi/clk-sunxi.c