OSDN Git Service

(root) / qmiga / qemu.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 8a0fc3a) | patch
target/arm: Implement HCR.PTW
authorPeter Maydell <peter.maydell@linaro.org>
Wed, 24 Oct 2018 06:50:18 +0000 (07:50 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Wed, 24 Oct 2018 06:51:36 +0000 (07:51 +0100)
commiteadb2febf05452bd8062c4c7823d7d789142500c
tree5863f36441121ee9ce5130a0c94f675b9a194ac4tree | snapshot
parent8a0fc3a29fc2315325400c738f807d0d4ae0ab7fcommit | diff
target/arm: Implement HCR.PTW

If the HCR_EL2 PTW virtualizaiton configuration register bit
is set, then this means that a stage 2 Permission fault must
be generated if a stage 1 translation table access is made
to an address that is mapped as Device memory in stage 2.
Implement this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181012144235.19646-8-peter.maydell@linaro.org
target/arm/helper.c diff | blob | history
About OSDN
Find Software
Develop Software
Help