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author	Craig Topper <craig.topper@intel.com>
	Tue, 13 Feb 2018 04:19:26 +0000 (04:19 +0000)
committer	Craig Topper <craig.topper@intel.com>
	Tue, 13 Feb 2018 04:19:26 +0000 (04:19 +0000)
commit	ebf3d94ea57b643450c3406d035769c3b7028529
tree	546c41fe7027d8193e853649948171e1b12cab37	tree \| snapshot
parent	7bdbf6e4d2bd80ebea6464e5f40a3df8f9410858	commit \| diff

[X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass.

Bits 7:4 control the scale part of the operation. If the scale is 0 the behavior is equivalent to VROUND.

Fixes PR36246

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324985 91177308-0d34-0410-b5e6-96231b3b80d8

12 files changed:

external/llvm

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lib/Target/X86/X86EvexToVex.cpp		diff \| blob \| history
test/CodeGen/X86/avx-intrinsics-x86.ll		diff \| blob \| history
test/CodeGen/X86/avx-schedule.ll		diff \| blob \| history
test/CodeGen/X86/avx512-intrinsics.ll		diff \| blob \| history
test/CodeGen/X86/avx512-scalar.ll		diff \| blob \| history
test/CodeGen/X86/avx512vl-intrinsics.ll		diff \| blob \| history
test/CodeGen/X86/rounding-ops.ll		diff \| blob \| history
test/CodeGen/X86/sse41-intrinsics-x86.ll		diff \| blob \| history
test/CodeGen/X86/sse41-schedule.ll		diff \| blob \| history
test/CodeGen/X86/vec_floor.ll		diff \| blob \| history
test/CodeGen/X86/vec_ss_load_fold.ll		diff \| blob \| history
utils/TableGen/X86EVEX2VEXTablesEmitter.cpp		diff \| blob \| history