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[MI scheduler] Fix VADD and VSUB in cortex-a57 model
authorEugene Leviant <eleviant@accesssoftek.com>
Tue, 21 Nov 2017 11:01:28 +0000 (11:01 +0000)
committerEugene Leviant <eleviant@accesssoftek.com>
Tue, 21 Nov 2017 11:01:28 +0000 (11:01 +0000)
commitec5c18ff129ffcf993e92f3a3aa2d6abf99a4563
tree2523797ea43d5274aca2306498463c7cddb0cbe5
parent09a18aac31f3bed46813da956ed2546764cbb210
[MI scheduler] Fix VADD and VSUB in cortex-a57 model

This patch fixes instregex for interger vector add/sub instructions

Differential revision: https://reviews.llvm.org/D40254

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318749 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMScheduleA57.td
test/CodeGen/ARM/cortex-a57-misched-vadd.ll [new file with mode: 0644]
test/CodeGen/ARM/cortex-a57-misched-vsub.ll [new file with mode: 0644]