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[AArch64][SVE] Add bfloat16 support to store intrinsics
authorKerry McLaughlin <kerry.mclaughlin@arm.com>
Fri, 26 Jun 2020 09:47:18 +0000 (10:47 +0100)
committerKerry McLaughlin <kerry.mclaughlin@arm.com>
Fri, 26 Jun 2020 10:05:56 +0000 (11:05 +0100)
commitedcfef8fee134cf98e0e812a6569c4900045d31c
treeae5737b6ccb31df6b123463587c7276526bb142e
parent1b10c618e9283104ad1e0de6e694982b5c942afd
[AArch64][SVE] Add bfloat16 support to store intrinsics

Summary:
Bfloat16 support added for the following intrinsics:
 - ST1
 - STNT1

Reviewers: sdesmalen, c-rhodes, fpetrogalli, efriedma, stuij, david-arm

Reviewed By: fpetrogalli

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D82448
14 files changed:
clang/include/clang/Basic/arm_sve.td
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c [new file with mode: 0644]
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1-bfloat.c [new file with mode: 0644]
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-reg.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-st1.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll