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radeonsi: only flush the right set of caches for CP DMA operations
authorMarek Olšák <marek.olsak@amd.com>
Mon, 29 Dec 2014 13:45:49 +0000 (14:45 +0100)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 7 Jan 2015 11:06:43 +0000 (12:06 +0100)
commitedf18da85dd3b1865c4faaba650a8fa371b7103c
tree5cf04bf87559911e77dd5c57093bb2d64503e390
parent73c2b0d18c51459697d8ec194ecfc4438c98c139
radeonsi: only flush the right set of caches for CP DMA operations

That's either framebuffer caches or caches for shader resources.
The motivation is that framebuffer caches need to be flushed very rarely
here.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
src/gallium/drivers/r600/r600_blit.c
src/gallium/drivers/radeon/r600_pipe_common.c
src/gallium/drivers/radeon/r600_pipe_common.h
src/gallium/drivers/radeon/r600_texture.c
src/gallium/drivers/radeon/radeon_video.c
src/gallium/drivers/radeonsi/si_blit.c
src/gallium/drivers/radeonsi/si_descriptors.c
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/drivers/radeonsi/si_state.h